This invention relates to an adder required for two-step parallel A/D conversion in which the lower bits are converted in overlapping the upper bit overlaps the lower bit in order to make more precise.
An adder used in this field of application has a circuit construction as described in, for example, Semiconductor Data Book, ECL by Hitachi Ltd., pp. 102-104, 3/1982 and has already been commercialized.
This known adder comprises, as shown in FIG. 6 of the accompanying drawings, an exclusive OR gate 701, an inverter 702, AND gates 703 to 707 and OR gates 708 and 709. The exclusive OR (NOR) gate 701 is adapted to decide whether the sum of two input signals A and B is "0" or "1", and the AND gates 703 and 704 and OR gate 708 operate to decide the sum of the decision result delivered from the gate 701 and a carry-in Ci from the lower digit. Any two of the three input signals A, B and Ci are applied to the AND gates 705 to 707, respectively, to produce a carry-out Co which assumes "1" when the two input signals are all "1".
Disadvantageously, the above prior art requires the delay time corresponding to three stages of logic gates and the gate delay time puts restrictions on the operation time of the adder. Further, the sum, designated by S, and the carry-out Co are decided and delivered independently of each other, whereby the sum S is delivered through three stages of gates and the carry-out Co through two stages of gates. Therefore, the propagation delay time is different for the sum S and carry-out Co and these signals must be brought into timed relationship in order for them to be applied to the succeeding logic gate. Furthermore, the number of component elements is large and the prior art adder is unsuitable for use as a component element of an LSI to be formed on a chip.